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2.7 ADC Input Channel Select Sequencing Control Registers

ADC Input Channel Select Sequencing Control Registers

Figure 2-9. ADC Input Channel Select Sequencing Control Registers (ADCCHSELSEQ1) (Address

Offset 03h)

15 12 11 8 7 4 3 0

CONV03 CONV02 CONV01 CONV00

R/W-0 R/W-0 R/W-0 R/W-0

LEGEND: R/W = Read/Write; - n = value after reset

Figure 2-10. ADC Input Channel Select Sequencing Control Registers (ADCCHSELSEQ2) (Address

Offset 04h)

15 12 11 8 7 4 3 0

CONV07 CONV06 CONV05 CONV04

R/W-0 R/W-0 R/W-0 R/W-0

LEGEND: R/W = Read/Write; - n = value after reset

Figure 2-11. ADC Input Channel Select Sequencing Control Registers (ADCCHSELSEQ3) (Address

Offset 05h)

15 12 11 8 7 4 3 0

CONV11 CONV10 CONV09 CONV08

R/W-0 R/W-0 R/W-0 R/W-0

LEGEND: R/W = Read/Write; - n = value after reset

Figure 2-12. ADC Input Channel Select Sequencing Control Registers (ADCCHSELSEQ4) (Address

Offset 06h)

15 12 11 8 7 4 3 0

CONV15 CONV14 CONV13 CONV12

R/W-0 R/W-0 R/W-0 R/W-0

LEGEND: R/W = Read/Write; - n = value after reset

Each of the 4-bit fields, CONVxx, selects one of the 16 MUXed analog input ADC channels for an

autosequenced conversion.

Table 2-11. CONVnn Bit Values and the ADC Input

Channels Selected

CONVnn Value ADC Input Channel Selected

0000 ADCINA0

0001 ADCINA1

0010 ADCINA2

0011 ADCINA3

0100 ADCINA4

0101 ADCINA5

0110 ADCINA6

0111 ADCINA7

1000 ADCINB0

1001 ADCINB1

1010 ADCINB2

1011 ADCINB3

1100 ADCINB4

44 ADC Registers SPRU812A – September 2007 – Revised October 2007

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