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ADC Control Registers

Table 2-2. ADC Control Register 2 (ADCTRL2) Field Descriptions (continued)

Bit(s) Name Value Description

5 SOC_SEQ2 Start of conversion trigger for sequencer 2 (SEQ2). (Only applicable in dual-sequencer

mode; ignored in cascaded mode.) This bit can be set by the following triggers:

• S/W - Software writing of 1 to this bit

• ePWM SOCB

When a trigger occurs, there are three possibilities:

Case 1: SEQ2 idle and SOC bit clear SEQ2 starts immediately (under arbiter control) and

the bit is cleared, allowing for any pending trigger requests.

Case 2: SEQ2 busy and SOC bit clear Bit is set signifying a trigger request is pending.

When SEQ2 finally starts after completing current conversion, this bit will be cleared.

Case 3: SEQ2 busy and SOC bit set Any trigger occurring in this case will be ignored

(lost).

0 Clears a Pending SOC trigger

Note: If the sequencer has already started, this bit is automatically cleared, and writing a

zero has no effect; i.e., an already started sequencer cannot be stopped by clearing this

bit.

1 Starts SEQ2 from currently stopped position (i.e., Idle mode)

4 Reserved Reads return a zero. Writes have no effect.

3 INT_ENA_SEQ2 SEQ2 interrupt enable. This bit enables or disables an interrupt request to the CPU by

INT SEQ2.

0 Interrupt request by INT_SEQ2 is disabled.

1 Interrupt request by INT_SEQ2 is enabled.

2 INT_MOD_SEQ2 SEQ2 interrupt mode. This bit selects SEQ2 interrupt mode. It affects the setting of INT

SEQ2 at the end of the SEQ2 conversion sequence.

0 INT_SEQ2 is set at the end of every SEQ2 sequence.

1 INT_SEQ2 is set at the end of every other SEQ2 sequence.

1 Reserved Reads return a zero. Writes have no effect.

0 ePWM_SOCB_SEQ2 ePWM SOCB enable bit for SEQ2.

0 SEQ2 cannot be started by ePWMx SOCB trigger.

1 Allows SEQ2 to be started by ePWMx SOCB trigger. The ePWMs can be programmed to

start a conversion on various events.

Figure 2-3. ADC Control Register 3 (ADCTRL3) (Address Offset 18h)

15 8

Reserved

R-0

7 6 5 4 1 0

ADCBGRFDN ADCPWDN ADCCLKPS SMODE_SEL

R/W-0 R/W-0 R/W-0 R/W-0

LEGEND: R/W = Read/Write; R = Read only; - n = value after reset

Table 2-3. ADC Control Register 3 (ADCTRL3) Field Descriptions

Bit(s) Name Value Description

15-8 Reserved Reads return a zero. Writes have no effect.

7-6 ADCBGRFDN[1:0] ADC bandgap and reference power down. These bits control the power up and power

down of the bandgap and reference circuitry inside the analog core. See Section 1.6 for

power-up sequence requirements.

00 The bandgap and reference circuitry is powered down.

11 The bandgap and reference circuitry is powered up.

5 ADCPWDN ADC power down. This bit controls the power up and power down of all the analog

circuitry inside the analog core except the bandgap and reference circuitry. See

Section 1.6 for power-up sequence requirements.

SPRU812A – September 2007 – Revised October 2007 ADC Registers 37

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