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1.3.2 Simultaneous Sampling Mode

1.3.3 Input Trigger Description

Uninterrupted Autosequenced Mode

Table 1-4. Values for ADCCHSELSEQn (MAX_CONV1 set to 2)

Bits 15-12 Bits 11-8 Bits 7-4 Bits 3-0

70A3h V

ADCCHSELSEQ1

70A4h x x V

ADCCHSELSEQ2

70A5h x x x x ADCCHSELSEQ3

70A6h x x x x ADCCHSELSEQ4

Table 1-5. Values After Second Autoconversion

Session

Buffer Register ADC Conversion Result Buffer

ADCRESULT0 I

ADCRESULT1 I

ADCRESULT2 I

ADCRESULT3 V

ADCRESULT4 V

ADCRESULT5 V

ADCRESULT6 x

ADCRESULT7 x

ADCRESULT8 x

ADCRESULT9 x

ADCRESULT10 x

ADCRESULT11 x

ADCRESULT12 x

ADCRESULT13 x

ADCRESULT14 x

ADCRESULT15 x

The ADC has the ability to sample two ADCINxx inputs simultaneously, provided that one input is from the

range ADCINA0 - ADCINA7 and the other input is from the range ADCINB0 - ADCINB7. Furthermore, the

two inputs must have the same sample-and-hold offset (i.e., ADCINA4 and ADCINB4, but not ADCINA7

and ADCINB6). To put the ADC into simultaneous sampling mode, the SMODE_SEL bit in the ADCTRL3

Each sequencer has a set of trigger inputs that can be enabled/disabled. See Table 1-6 for the valid input

triggers for SEQ1, SEQ2, and cascaded SEQ.

Table 1-6. Input Triggers

SEQ1 (sequencer 1) SEQ2 (sequencer 2) Cascaded SEQ

Software trigger (software SOC) Software trigger (software SOC) Software trigger (software SOC)

ePWMx SOCA ePWMx SOCB ePWMx SOCA

XINT2_ADCSOC ePWMx SOCB

XINT2_ADCSOC

SPRU812A – September 2007 – Revised October 2007 Analog-to-Digital Converter (ADC) 23

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