ADC 320F Spezifikationen PDF herunterladen (Seite 11)

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Result Registers

ePWMx SOCB

S/W

GPIO/XINT2_

ADCSOC

ePWMx SOCA

S/W

Sequencer 2Sequencer 1

SOCSOC

ADC Control Registers

70B7h

70B0h

70AFh

70A8h

Result Reg 15

Result Reg 8

Result Reg 7

Result Reg 1

Result Reg 0

module

ADC

12-Bit

Analog

MUX

ADCINA0

ADCINA7

ADCINB0

ADCINB7

System

control block

High-speed

prescaler

HSPCLK

C28x

SYSCLKOUT

S/H-A

S/H-B

ADCENCLK HALT

Features

Figure 1-1. Block Diagram of the ADC Module

Table 1-1. ADC Registers

Name Address

(1)

Address

(2)

Size (x16) Description

ADCTRL1 0x7100 1 ADC Control Register 1

ADCTRL2 0x7101 1 ADC Control Register 2

ADCMAXCONV 0x7102 1 ADC Maximum Conversion Channels Register

ADCCHSELSEQ1 0x7103 1 ADC Channel Select Sequencing Control Register 1

ADCCHSELSEQ2 0x7104 1 ADC Channel Select Sequencing Control Register 2

ADCCHSELSEQ3 0x7105 1 ADC Channel Select Sequencing Control Register 3

ADCCHSELSEQ4 0x7106 1 ADC Channel Select Sequencing Control Register 4

ADCASEQSR 0x7107 1 ADC Auto-Sequence Status Register

ADCRESULT0 0x7108 0x0B00 1 ADC Conversion Result Buffer Register 0

ADCRESULT1 0x7109 0x0B01 1 ADC Conversion Result Buffer Register 1

ADCRESULT2 0x710A 0x0B02 1 ADC Conversion Result Buffer Register 2

ADCRESULT3 0x710B 0x0B03 1 ADC Conversion Result Buffer Register 3

ADCRESULT4 0x710C 0x0B04 1 ADC Conversion Result Buffer Register 4

ADCRESULT5 0x710D 0x0B05 1 ADC Conversion Result Buffer Register 5

ADCRESULT6 0x710E 0x0B06 1 ADC Conversion Result Buffer Register 6

ADCRESULT7 0x710F 0x0B07 1 ADC Conversion Result Buffer Register 7

ADCRESULT8 0x7110 0x0B00 1 ADC Conversion Result Buffer Register 8

ADCRESULT9 0x7111 0x0B09 1 ADC Conversion Result Buffer Register 9

(1)

The registers in this column are Peripheral Frame 2 registers.

(2)

The ADC result registers are dual mapped in the device. Locations in Peripheral Frame 2 (0x7108-0x7117) are 2 wait states

and left justified. Locations in Peripheral Frame 0 space (0x0B00-0x0B0F) are 0 wait states and right justified. During high

speed/continuous conversion use of the ADC, use the 0 wait state locations to avoid missing ADC conversions.

SPRU812A – September 2007 – Revised October 2007 Analog-to-Digital Converter (ADC) 11

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