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1.6 Power-up Sequence

1.7 Sequencer Override Feature

Power-up Sequence

Table 1-8. Power Options

Power Level ADCBGRFDN1 ADCBGRFDN0 ADCPWDN

ADC power-up 1 1 1

ADC power-down 1 1 0

ADC off 0 0 0

Reserved 1 0 X

Reserved 0 1 X

The ADC resets to the ADC off state. When powering up the ADC, use the following sequence:

1. If external reference is desired, enable this mode using bits 15-14 in the ADCREFSEL Register. This

mode must be enabled before band gap is powered.

2. Power up the reference, bandgap, and analog circuits together by setting bits 7-5 (ADCBGRFDN[1:0],

ADCPWDN) in the ADCTRL3 register.

3. Before performing the first conversion, a delay of 5 ms is required.

When powering down the ADC, all three bits can be cleared simultaneously. The ADC power level must

be controlled via software and they are independent of the state of the device power modes.

Sometimes it is desirable to power down the ADC while leaving the band-gap and reference powered by

clearing the ADCPWDN bit only. When the ADC is re-powered, a delay of 20 μ s is required after this bit is

set before performing any conversions.

Note: The 2833x ADC requires a 5-ms delay after all of the circuits are powered up. This differs

from the 281x ADC.

In normal operation, sequencers SEQ1, SEQ2 or cascaded SEQ1 help to convert selected ADC channels

and store them in the respective ADCRESULTn registers, sequentially. The sequence naturally wraps

around at the end of the MAX_CONVn setting. With the sequencer override feature, the natural

wraparound of the sequencers can be controlled in software. The sequencer override feature is controlled

by bit 5 of the ADC Control Register 1 (ADCCTRL1).

For example, assume the SEQ_OVRD bit is 0 and the ADC is in cascaded-sequencer,

continuous-conversion mode with MAX_CONV1 set to 7. Normally, the sequencer would increment

sequentially and update up to ADCRESULT7 register with ADC conversions and wraps around to 0. At the

end of the ADCRESULT7 register update, the relevant interrupt flag would be set.

With the SEQ_OVRD bit set to 1, the sequencer updates seven result registers and does not wrap around

to 0. Instead, the sequencer will increment sequentially and update the ADCRESULT8 register onwards

until the ADCRESULT15 register is reached. After updating ADCRESULT15 register, the natural wrap

around to 0 will occur. This feature treats the result registers (0-15) like a FIFO for sequential data capture

from the ADC. This feature is very helpful to capture ADC data when ADC conversions are done at the

maximum data rate.

SPRU812A – September 2007 – Revised October 2007 Analog-to-Digital Converter (ADC) 27

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ADC 320F Spezifikationen Seite 27