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1.3.4 Interrupt Operation During Sequenced Conversions

Uninterrupted Autosequenced Mode

Notes:

• An SOC trigger can initiate an autoconversion sequence whenever a sequencer is in an

idle state. An idle state is either CONV00 prior to receiving a trigger, or any state which

the sequencer lands on at the completion of a conversion sequence, i.e., when

SEQ_CNTR has reached a count of zero.

• If an SOC trigger occurs while a current conversion sequence is underway, it sets the

SOC_SEQn bit (which would have been cleared on the commencement of a previous

conversion sequence) in the ADCTRL2 register. If yet another SOC trigger occurs, it is

lost (i.e., when the SOC_SEQn bit is already set (SOC pending), subsequent triggers

will be ignored).

• Once triggered, the sequencer cannot be stopped/halted in mid sequence. The program

must either wait until an end-of-sequence (EOS) or initiate a sequencer reset, which

brings the sequencer immediately back to the idle start state (CONV00 for SEQ1 and

cascaded cases; CONV08 for SEQ2).

• When SEQ1/2 are used in cascaded mode, triggers going to SEQ2 are ignored, while

SEQ1 triggers are active. Cascaded mode can be viewed as SEQ1 with 16 states

instead of eight.

The sequencer can generate interrupts under two operating modes. These modes are determined by the

Interrupt-Mode-Enable control bits in ADCTRL2.

A variation of Example 1-4 can be used to show how interrupt mode 1 and mode 2 are useful under

different operating conditions.

Case 1: Number of samples in the first and second sequences are not equal

• Mode 1 Interrupt operation (i.e., Interrupt request occurs at every EOS)

1. Sequencer is initialized with MAX_CONVn = 1 for converting I

and I

2. At ISR "a", MAX_CONVn is changed to 2 (by software) for converting V

, V

, and V

3. At ISR "b", the following events take place :

a. MAX_CONVn is changed to 1 again for converting I

and I

b. Values I

, I

, V

, and V

are read from ADC result registers.

c. The sequencer is reset.

4. Steps 2 and 3 are repeated. Note that the interrupt flag is set every time SEQ_CNTR reaches zero

and both interrupts are recognized.

Case 2: Number of samples in the first and second sequences are equal

• Mode 2 Interrupt operation (i.e., Interrupt request occurs at every other EOS)

1. Sequencer is initialized with MAX_CONVn = 2 for converting I

, I

, and I

(or V

, V

, and V

2. At ISR "b" and "d", the following events take place :

a. Values I

, I

, V

, and V

are read from ADC result registers.

b. The sequencer is reset.

3. Step 2 is repeated.

Case 3: Number of samples in the first and second sequences are equal (with dummy read)

• Mode 2 Interrupt operation (i.e., Interrupt request occurs at every other EOS)

1. Sequencer is initialized with MAX_CONVn = 2 for I

, I

, and x(dummy sample).

2. At ISR "b" and "d", the following events take place :

a. Values I

, I

, x,V

, V

, and V

are read from ADC result registers.

b. The sequencer is reset.

3. Step 2 is repeated. Note that the third I-sample (x) is a dummy sample, and is not really required.

However, to minimize ISR overhead and CPU intervention, advantage is taken of the "every other"

Interrupt request feature of Mode 2.

24 Analog-to-Digital Converter (ADC) SPRU812A – September 2007 – Revised October 2007

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