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Uninterrupted Autosequenced Mode

Example 1-3. Conversion in Dual-Sequencer Mode Using SEQ1

Suppose seven conversions are desired from SEQ1 (i.e., inputs ADCINA2 and ADCINA3 twice, then

ADCINA6, ADCINA7, and ADCINB4 must be converted as part of the autosequenced session), then

MAX_CONV1 should be set to 6 and the ADCCHSELSEQn registers should be set to the values shown

in Table 1-3 .

Conversion begins once the start-of-conversion (SOC) trigger is received by the sequencer. The SOC

trigger also loads the SEQ_CNTR bits. Those channels that are specified in the ADCCHSELSEQn

registers are taken up for conversion, in the predetermined sequence. The SEQ_CNTR bits are

decremented by one automatically after every conversion. Once SEQ_CNTR reaches zero, two things

can happen, depending on the status of the continuous run bit (CONT_RUN) in the ADCTRL1 register.

See Figure 1-6 for an illustration of the flow.

• If CONT_RUN is set, the conversion sequence starts all over again automatically (i.e., SEQ_CNTR

gets reloaded with the original value in MAX_CONV1 and SEQ1 state is set to CONV00 [See

Section 1.7 for more options]). In this case, to avoid overwriting the data, you must be sure that the

result registers are read before the next conversion sequence begins. The arbitration logic designed

into the ADC ensures that the result registers are not corrupted should a contention arise (ADC

module trying to write into the result registers while you try to read from them at the same time).

• If CONT_RUN is not set, the sequencer stays in the last state (CONV06, in this example) and

SEQ_CNTR continues to hold a value of zero. To repeat the sequence on the next SOC, the

sequencer must be reset using the RST_SEQn bit prior to the next SOC.

If the interrupt flag is set every time SEQ_CNTR reaches zero (INT_ENA_SEQn = 1 and

INT_MOD_SEQn = 0), you can (if needed) manually reset the sequencer (using the RST_SEQn bit in

the ADCTRL2 register) in the interrupt service routine (ISR). This causes the SEQn state to be reset to

its original value (CONV00 for SEQ1 and CONV08 for SEQ2). This feature is useful in the Start/Stop

operation of the sequencer. Example 1-3 also applies to SEQ2 and the cascaded 16-state sequencer

(SEQ) with differences outlined in Table 1-2 .

Table 1-3. Values for ADCCHSELSEQn Registers (MAX_CONV1 Set to 6)

Bits 15-12

(1)

Bits 11-8

(1)

Bits 7-4

(1)

Bits 3-0

(1)

70A3h 3 2 3 2 ADCCHSELSEQ1

70A4h x 12 7 6 ADCCHSELSEQ2

70A5h x x x x ADCCHSELSEQ3

70A6h x x x x ADCCHSELSEQ4

(1)

Values are in decimal, and x = don't care

Analog-to-Digital Converter (ADC)20 SPRU812A – September 2007 – Revised October 2007

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