ADC 2 Bedienungsanleitung

REV. AInformation furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsu

REV. A–10–AD7866AVDD RIPPLE FREQUENCY – Hz0–1001kPSRR – dB10k–90–80–70–60–50–40–30–20–10100k 1M100mV p-p SINE WAVE ON AVDD2.5V EXT REFERENCE ON VREFTA

REV. AAD7866–11–CIRCUIT INFORMATIONThe AD7866 is a fast, micropower, dual 12-bit, single supply,A/D converter that operates from a 2.7 V to 5.25 V sup

REV. A–12–AD7866Analog Input RangesThe analog input range for the AD7866 can be selected to be 0 Vto VREF or 2  VREF with either straight binary or t

REV. AAD7866–13–CSSCLKRANGEDOUTADOUTB1816 161ABVREF/2 ⴞ VREF/2INPUT RANGETWOS COMPLEMENTFigure 7. Selecting VREF/2 ± VREF/2 Input Range with Twos Comp

REV. A–14–AD7866Digital InputsThe digital inputs applied to the AD7866 are not limited by themaximum ratings that limit the analog inputs. Instead, th

REV. AAD7866–15–100nF2.5VREFADC BEXT REFEXT REF470nFDCAPBDCAPAVREFEXT REF470nFBUF BADC ABUF AFigure 15. Reference CircuitIf the on-chip 2.5 V referenc

REV. A–16–AD7866terminated, and DOUTA and DOUTB will go back into three-state. If CS is brought high before the second SCLK fallingedge, the part will

REV. AAD7866–17–CS116102THREE-STATESCLKDOUTADOUTBFigure 17. Entering Partial Power-Down Mode11610116INVALID DATA VALID DATACSSCLKDOUTADOUTBTHE PART BE

REV. A–18–AD7866POWER VS. THROUGHPUT RATEWhen the AD7866 is in partial power-down mode and notconverting, the average power consumption of the ADC dec

REV. AAD7866–19–DOUTA. Likewise, if CS is held low for a further 16 SCLK cycleson DOUTB, the data from conversion A will be output on DOUTB.This is il

REV. A–2–AD7866–SPECIFICATIONS(TA = TMIN to TMAX, VDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, Reference = 2.5 VExternal on DCAPA and DCAPB, fSCLK

REV. A–20–AD7866For example, if the ADSP-2189 had a 20 MHz crystal such that ithad a master clock frequency of 40 MHz, then the master cycletime would

REV. AAD7866–21–etch technique is generally best for ground planes because it givesthe best shielding. Both AGND pins of the AD7866 should besunk in t

REV. A–22–AD7866OUTLINE DIMENSIONS20-Lead Thin Shrink Small Outline Package [TSSOP](RU-20)Dimensions shown in millimeters20111106.40 BSC4.504.404.30PI

REV. AAD7866–23–Revision HistoryLocation Page2/03—Data Sheet changed from REV. 0 to REV. A.Addition to FEATURES . . . . . . . . . . . . . . . . . . .

C02672–0–2/03(A)PRINTED IN U.S.A.–24–

REV. AAD7866–3–Parameter A Version1B Version1Unit Test Conditions/CommentsCONVERSION RATEConversion Time 16 16 SCLK cycles 800 ns with SCLK = 20 MHzTr

REV. A–4–AD7866TIMING SPECIFICATIONS1(VDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V; TA = TMIN to TMAX, unless otherwise noted.)Limit

REV. AAD7866–5–ORDERING GUIDEResolution PackageModel Temperature Range (Bits) Package Description OptionAD7866ARU –40°C to +125°C12Thin Shrink SOC (TS

REV. A–6–AD7866PIN CONFIGURATIONTOP VIEW(Not to Scale)2019181716151413121112345678910AD7866REF SELECTA0DCAPBAGNDVB2VB1VA2VA1AGNDDCAPAVREFCSSCLKVDRIVED

REV. AAD7866–7–PIN FUNCTION DESCRIPTIONS (continued)Pin No. Mnemonic Function11 RANGE Analog Input Range and Output Coding Selection. Logic input. The

REV. A–8–AD7866TERMINOLOGYIntegral NonlinearityThis is the maximum deviation from a straight line passingthrough the endpoints of the ADC transfer fun

REV. AAD7866–9–Typical Performance CharacteristicsFREQUENCY – kHz0–35–1150 500100SNR – dB200 300 400–55–75–9550 150 250 350 4504098 POINT FFTfSAMPLE =