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2.2 Maximum Conversion Channels Register (ADCMAXCONV)

Maximum Conversion Channels Register (ADCMAXCONV)

Table 2-3. ADC Control Register 3 (ADCTRL3) Field Descriptions (continued)

Bit(s) Name Value Description

0 All analog circuitry inside the core except the bandgap and reference circuitry is powered

down.

1 The analog circuitry inside the core is powered up.

4-1 ADCCLKPS [3:0] Core clock divider. 28x peripheral clock, HSPCLK, is divided by 2*ADCCLKPS[3-0],

except when ADCCLKPS[3-0] is 0000, in which case HSPCLK is directly passed on. The

divided clock is further divided by ADCTRL1[7]+1 to generate the core clock, ADCLK.

ADCCLKPS [3:0] Core Clock Divider ADCLK

0000 0 HSPCLK/(ADCTRL1[7] + 1)

0001 1 HSPCLK/[2*(ADCTRL1[7] + 1)]

0010 2 HSPCLK/[4*(ADCTRL1[7] + 1)]

0011 3 HSPCLK/[6*(ADCTRL1[7] + 1)]

0100 4 HSPCLK/[8*(ADCTRL1[7] + 1)]

0101 5 HSPCLK/[10*(ADCTRL1[7] + 1)]

0110 6 HSPCLK/[12*(ADCTRL1[7] + 1)]

0111 7 HSPCLK/[14*(ADCTRL1[7] + 1)]

1000 8 HSPCLK/[16*(ADCTRL1[7] + 1)]

1001 9 HSPCLK/[18*(ADCTRL1[7] + 1)]

1010 10 HSPCLK/[20*(ADCTRL1[7] + 1)]

1011 11 HSPCLK/[22*(ADCTRL1[7] + 1)]

1100 12 HSPCLK/[24*(ADCTRL1[7] + 1)]

1101 13 HSPCLK/[26*(ADCTRL1[7] + 1)]

1110 14 HSPCLK/[28*(ADCTRL1[7] + 1)]

1111 15 HSPCLK/[30*(ADCTRL1[7] + 1)]

0 SMODE_SEL Sampling mode select. This bit selects either sequential or simultaneous sampling mode.

0 Sequential sampling mode is selected.

1 Simultaneous sampling mode is selected.

Figure 2-4. Maximum Conversion Channels Register (ADCMAXCONV) (Offset Address 02h)

15 8

Reserved

R-0

7 6 4 3 0

Reserved MAX_CONV2 MAX_CONV1

R-0 R/W-0 R/W-0

LEGEND: R/W = Read/Write; R = Read only; x = undefined, - n = value after reset

ADC Registers38 SPRU812A – September 2007 – Revised October 2007

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ADC 320F Spezifikationen Seite 38