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Autoconversion Sequencer Principle of Operation

Table 1-2. Comparison of Single and Cascaded Operating Modes

Single 8-state sequencer #1 Single 8-state Cascaded 16-state

Feature (SEQ1) sequencer #2 (SEQ2) sequencer (SEQ)

Start-of-conversion (SOC) ePWMx SOCA, software, ePWMx SOCB, software ePWMx SOCA, ePWMx

triggers external pin SOCB, software,

external pin

Maximum number of 8 8 16

autoconversions

(i.e., sequence length)

Autostop at end-of- Yes Yes Yes

sequence (EOS)

Arbitration priority High Low Not applicable

ADC conversion result register 0 to 7 8 to 15 0 to 15

locations

ADCCHSELSEQn bit field CONV00 to CONV07 CONV08 to CONV15 CONV00 to CONV15

assignment

For convenience, the sequencer states will be subsequently referred to as:

• For SEQ1: CONV00 to CONV07

• For SEQ2: CONV08 to CONV15

• For Cascaded SEQ: CONV00 to CONV15

The analog input channel selected for each sequenced conversion is defined by CONVxx bit fields in the

ADC input channel select sequencing control registers (ADCCHSELSEQn). CONVxx is a 4-bit field that

specifies any one of the 16 channels for conversion. Since a maximum of 16 conversions in a sequence is

possible when using the sequencers in cascaded mode, 16 such 4-bit fields (CONV00 - CONV15) are

available and are spread across four 16-bit registers (ADCCHSELSEQ1 - ADCCHSELSEQ4). The

CONVxx bits can have any value from 0 to 15. The analog channels can be chosen in any desired order

and the same channel may be selected multiple times.

SPRU812A – September 2007 – Revised October 2007 Analog-to-Digital Converter (ADC) 17

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ADC 320F Spezifikationen Seite 17