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List of Figures

1-1 Block Diagram of the ADC Module ...................................................................................... 11

1-2 Sequential Sampling Mode (SMODE = 0) .............................................................................. 13

1-3 Simultaneous Sampling Mode (SMODE=1) ............................................................................ 14

1-4 Block Diagram of Autosequenced ADC in Cascaded Mode ......................................................... 15

1-5 Block Diagram of Autosequenced ADC With Dual Sequencers .................................................... 16

1-6 Flow Chart for Uninterrupted Autosequenced Mode .................................................................. 21

1-7 Example of ePWM Triggers to Start the Sequencer .................................................................. 22

1-8 Interrupt Operation During Sequenced Conversions ................................................................. 25

1-9 ADC Core Clock and Sample-and-Hold (S/H) Clock .................................................................. 26

1-10 Clock Chain to the ADC ................................................................................................... 26

1-11 External Bias for 2.048-V External Reference .......................................................................... 30

1-12 Flow Chart of Offset Error Correction Process ......................................................................... 31

1-13 Ideal Code Distribution of Sampled 0-V Reference .................................................................... 32

2-1 ADC Control Register 1 (ADCTRL1) (Address Offset 00h) ........................................................... 34

2-2 ADC Control Register 2 (ADCTRL2) (Address Offset 01h) ........................................................... 35

2-3 ADC Control Register 3 (ADCTRL3) (Address Offset 18h) ........................................................... 37

2-4 Maximum Conversion Channels Register (ADCMAXCONV) (Offset Address 02h) .............................. 38

2-5 Autosequence Status Register (ADCASEQSR) (Address Offset 07h) .............................................. 40

2-6 ADC Status and Flag Register (ADCST) (Address Offset 19h) ...................................................... 41

2-7 ADC Reference Select Register (ADCREFSEL) (Address Offset 1Ch) ............................................. 43

2-8 ADC Offset Trim Register (ADCOFFTRIM) (Address Offset 1Dh) .................................................. 43

2-9 ADC Input Channel Select Sequencing Control Registers (ADCCHSELSEQ1) (Address Offset 03h) ......... 44

2-10 ADC Input Channel Select Sequencing Control Registers (ADCCHSELSEQ2) (Address Offset 04h) ......... 44

2-11 ADC Input Channel Select Sequencing Control Registers (ADCCHSELSEQ3) (Address Offset 05h) ......... 44

2-12 ADC Input Channel Select Sequencing Control Registers (ADCCHSELSEQ4) (Address Offset 06h) ......... 44

2-13 ADC Conversion Result Buffer Registers (ADCRESULTn) - (Addresses 0x7108-0x7117) ...................... 45

2-14 ADC Conversion Result Buffer Registers (ADCRESULTn) - (Addresses 0x0B00-0x0B0F) ..................... 45

4 List of Figures SPRU812A – September 2007 – Revised October 2007

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ADC 320F Spezifikationen Seite 4