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2.5 ADC Reference Select Register (ADCREFSEL)

2.6 ADC Offset Trim Register (ADCOFFTRIM)

ADC Reference Select Register (ADCREFSEL)

Figure 2-7. ADC Reference Select Register (ADCREFSEL) (Address Offset 1Ch)

15 14 13 0

REF_SEL Reserved

R/W-0 R/W-0

LEGEND: R/W = Read/Write; R = Read only; - n = value after reset

Table 2-9. ADC Reference Select Register (ADCREFSEL) Field Descriptions

Bit(s) Name Value Description

15-14 REF_SEL[1:0] Reference select bits for ADC voltage generation circuit options are listed below:

00 Internal reference selected (default)

01 External reference, 2.048 V on ADCREFIN

10 External reference, 1.500 V on ADCREFIN

11 External reference, 1.024 V on ADCREFIN

13-0 Reserved These bits are reserved for reference calibration data loaded from the Boot ROM. All

writes to the ADCREFSEL register should leave the contents of this bit field as is after

population by the Boot ROM.

Figure 2-8. ADC Offset Trim Register (ADCOFFTRIM) (Address Offset 1Dh)

15 9 8 0

Reserved OFFSET_TRIM

R-0 R/W-0

LEGEND: R/W = Read/Write; R = Read only; - n = value after reset

Table 2-10. ADC Offset Trim Register (ADCOFFTRIM) Field Descriptions

Bit(s) Name Description

15-9 Reserved Reads return a zero. Writes have no effect.

8-0 OFFSET_TRIM[8:0] Offset trim value in LSBs, two's complement format; - 256/255 range

SPRU812A – September 2007 – Revised October 2007 ADC Registers 43

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ADC 320F Spezifikationen Seite 43