ADC 320F Spezifikationen PDF herunterladen (Seite 13)

www.ti.com

1.2.1 Sequential Sampling Mode

Variable-width

acquisition window

ADC

Clock

[C0NV00]

†

[C0NV00]

†

S C1

ADC SOC

trigger

Legend: C1 − Duration of time for result register update

S − Acquisition window

Channel

Select

SH Clock

[C0NV01]

(A)

Autoconversion Sequencer Principle of Operation

sampling mode, the MSB of the CONVxx register is discarded. Each sample and hold buffer samples the

associated pin given by the offset provided in the three LSBs of the CONVxx register. For instance, if the

CONVxx register contains the value 0110b, ADCINA6 is sampled by S/H-A and ADCINB6 is sampled by

S/H-B. If the value is 1001b, ADCINA1 is sampled by S/H-A and ADCINB1 is sampled by S/H-B. The

voltage in S/H-A is converted first, followed by the S/H-B voltage. The result of the S/H-A conversion is

placed in the current ADCRESULTn register (ADCRESULT0 for SEQ1, assuming the sequencer has been

reset). The result of the S/H-B conversion is placed in the next ADCRESULTn register (ADCRESULT1 for

SEQ1, assuming the sequencer has been reset). The result register pointer is then increased by two (to

point to ADCRESULT2 for SEQ1, assuming the sequencer had originally been reset).

Figure 1-2 shows the timing of sequential sampling mode. In this example, the ACQ_PS bits are set to

0001b.

Figure 1-2. Sequential Sampling Mode (SMODE = 0)

A ADC channel address contained in [CONV00] 4-bit register; CONV00 for SEQ1 and CONV08 for SEQ2.

SPRU812A – September 2007 – Revised October 2007 Analog-to-Digital Converter (ADC) 13

Submit Documentation Feedback

1 2 ... 8 9 10 11 12 13 14 15 16 17 18 ... 45 46

Keine Kommentare

ADC 320F Spezifikationen Seite 13