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1.11 ADC to DMA Interface

ADC to DMA Interface

Figure 1-13. Ideal Code Distribution of Sampled 0-V Reference

The ADC result registers located in peripheral frame 0 (0x0B00 – 0x0B0F) are accessible by the DMA unit

on the F2833x. These registers can also be accessed by the CPU at the same time as the DMA without

bus contention. The result registers in peripheral frame 2 (0x7108 – 0x710F) are not accessible by the

DMA.

There is a sync signal provided automatically by the ADC to the DMA for a sequencer 1 conversion when

both SEQ_OVRD and CONT_RUN bits are set. The sync pulse will be generated by the ADC after the

first MAXCONV limit is reached for each pass through the sequencer. When the sequencer 1 is in this

configuration it is possible that the DMA could become misaligned to the currently populated result

registers, depending on the loading of the other DMA channels. If a misalignment occurs, the DMA can

use the sync signal to detect and flag a sync error event.

For more information on how the sync signal is used locally in the DMA, please see the TMS320F2833x

Direct Memory Access (DMA) Reference Guide (literature number SPRUFB8 ).

32 Analog-to-Digital Converter (ADC) SPRU812A – September 2007 – Revised October 2007

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ADC 320F Spezifikationen Seite 32