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ADC12D1800RF

www.ti.com

SNAS518I –JULY 2011–REVISED JANUARY 2014

Table 6-5. Supported Demux, Data Rate Modes

Non-Demux Mode 1:2 Demux Mode

DDR 0° Mode only 0° Mode / 90° Mode

SDR Not Available Rising / Falling Mode

6.3.2.6 Test Pattern Mode

The ADC12D1800RF can provide a test pattern at the four output buses independently of the input signal

to aid in system debug. In Test Pattern Mode, the ADC is disengaged and a test pattern generator is

connected to the outputs, including ORI and ORQ. The test pattern output is the same in DES Mode or

Non-DES Mode. Each port is given a unique 12-bit word, alternating between 1's and 0's. When the part is

programmed into the Demux Mode, the test pattern’s order is described in Table 6-6. If the I- or Q-channel

is powered down, the test pattern will not be output for that channel.

Table 6-6. Test Pattern by Output Port in

Demux Mode

(1)

Time Qd Id Q I ORQ ORI Comments

T0 000h 004h 008h 010h 0b 0b

T1 FFFh FFBh FF7h FEFh 1b 1b

Pattern

T2 000h 004h 008h 010h 0b 0b Sequence

T3 FFFh FFBh FF7h FEFh 1b 1b

T4 000h 004h 008h 010h 0b 0b

T5 000h 004h 008h 010h 0b 0b

T6 FFFh FFBh FF7h FEFh 1b 1b

Pattern

T7 000h 004h 008h 010h 0b 0b Sequence

n+1

T8 FFFh FFBh FF7h FEFh 1b 1b

T9 000h 004h 008h 010h 0b 0b

T10 000h 004h 008h 010h 0b 0b

Pattern

T11 FFFh FFBh FF7h FEFh 1b 1b

Sequence

T12 000h 004h 008h 010h 0b 0b

n+2

T13 ... ... ... ... ... ...

(1) When the part is programmed into the Non-Demux Mode, the test pattern’s order is described in Table 6-7.

Table 6-7. Test Pattern by Output Port in

Non-Demux Mode

Time Q I ORQ ORI Comments

T0 000h 004h 0b 0b

T1 000h 004h 0b 0b

T2 FFFh FFB h 1b 1b

T3 FFFh FFB h 1b 1b

Pattern

T4 000h 004h 0b 0b

Sequence

T5 FFFh FFB h 1b 1b

T6 000h 004h 0b 0b

T7 FFFh FFB h 1b 1b

T8 FFFh FFB h 1b 1b

T9 FFFh FFB h 1b 1b

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