ADC 6 Spezifikationen PDF herunterladen (Seite 15)

GND

100 k:

GND

100 k:

GND

50 k:

GND

ADC12D1800RF

www.ti.com

SNAS518I –JULY 2011–REVISED JANUARY 2014

Table 2-2. Control and Status Balls (continued)

Ball No. Name Equivalent Circuit Description

Full-Scale input Range select. In Non-ECM, this

input must be set to logic-high; the full-scale

differential input range for both I- and Q-channel

inputs is set by this pin. In the ECM, this input is

ignored and the full-scale range of the I- and Q-

Y3 FSR

channel inputs is independently determined by the

setting of Addr: 3h and Addr: Bh, respectively.

Note that the logic-high FSR value in Non-ECM

corresponds to the minimum allowed selection in

ECM.

DDR Phase select. This input, when logic-low,

selects the 0° Data-to-DCLK phase relationship.

When logic-high, it selects the 90° Data-to-DCLK

phase relationship, i.e. the DCLK transition

indicates the middle of the valid data outputs. This

W4 DDRPh pin only has an effect when the chip is in 1:2

Demuxed Mode, i.e. the NDM pin is set to logic-

low. In ECM, this input is ignored and the DDR

phase is selected through the Control Register by

the DPS Bit (Addr: 0h, Bit 14); the default is 0°

Mode.

Extended Control Enable bar. Extended feature

control through the SPI interface is enabled when

this signal is asserted (logic-low). In this case,

most of the direct control pins have no effect.

B3 ECE

When this signal is de-asserted (logic-high), the

SPI interface is disabled, all SPI registers are

reset to their default values, and all available

settings are controlled via the control pins.

Serial Chip Select bar. In ECM, when this signal is

asserted (logic-low), SCLK is used to clock in

serial data which is present on SDI and to source

C4 SCS

serial data on SDO. When this signal is de-

asserted (logic-high), SDI is ignored and SDO is in

TRI-STATE.

Serial Clock. In ECM, serial data is shifted into

and out of the device synchronously to this clock

C5 SCLK signal. This clock may be disabled and held logic-

low, as long as timing specifications are not

violated when the clock is enabled or disabled.

Submit Documentation Feedback

Product Folder Links: ADC12D1800RF

1 2 ... 10 11 12 13 14 15 16 17 18 19 20 ... 79 80

Kommentare zu diesen Handbüchern

Keine Kommentare

ADC 6 Spezifikationen Seite 15

Kommentare zu diesen Handbüchern

Verwandte Produkte und Handbücher für Vernetzung ADC 6