ADC 6 Spezifikationen PDF herunterladen (Seite 17)

DR GND

ADC12D1800RF

www.ti.com

SNAS518I –JULY 2011–REVISED JANUARY 2014

Table 2-3. Power and Ground Balls (continued)

Ball No. Name Equivalent Circuit Description

A1, A7, B2, B7,

D4, D5, E4, K1,

L1, T4, U4, U5, GND NONE Ground Return for the Analog circuitry.

W2, W7, Y1, Y7,

H8:N13

F2, G2, H3, J2,

K4, L4, M2, N3, Ground Return for the Track-and-Hold and Clock

GND

NONE

P2, R2, T2, T3, circuitry.

A13, A17, A20,

D13, D16, E17,

F17, F20, M17,

GND

NONE Ground Return for the Output Drivers.

M20, U13, U17,

V18, Y13, Y17,

Y20

A9, B8, C9, V9,

GND

NONE Ground Return for the Digital Encoder.

W8, Y9

Table 2-4. High-Speed Digital Outputs

Ball No. Name Equivalent Circuit Description

Data Clock Output for the I- and Q-channel data

bus. These differential clock outputs are used to

latch the output data and, if used, should always

be terminated with a 100Ω differential resistor

placed as closely as possible to the differential

receiver. Delayed and non-delayed data outputs

K19/K20 DCLKI+/-

are supplied synchronously to this signal. In 1:2

L19/L20 DCLKQ+/-

Demux Mode or Non-Demux Mode, this signal is

at ¼ or ½ the sampling clock rate, respectively.

DCLKI and DCLKQ are always in phase with each

other, unless one channel is powered down, and

do not require a pulse from DCLK_RST to

become synchronized.

Out-of-Range Output for the I- and Q-channel.

This differential output is asserted logic-high while

the over- or under-range condition exists, i.e. the

differential signal at each respective analog input

K17/K18 ORI+/- exceeds the full-scale value. Each OR result

L17/L18 ORQ+/- refers to the current Data, with which it is clocked

out. If used, each of these outputs should always

be terminated with a 100Ω differential resistor

placed as closely as possible to the differential

receiver. ORQ

(1)

(1) This pin / bit functionality is not tested in production test; performance is tested in the specified / default mode only.

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