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DB[11:0]

b01xxxxx001

DAC lVa ue

b01xxxxx011 DAC lVa ue

ADS7865

www.ti.com

SBAS441C –OCTOBER 2008–REVISED APRIL 2012

Programming the Reference DAC

To verify the current DAC setting, a WR pulse must

be generated while providing a control word

The internal reference DAC can be set by issuing a

containing R[1:0] = '01' and A[2:0] = '011' to initialize

WR pulse while providing a control word with R[1:0] =

the DAC read access. Thereafter, triggering the RD

'01' and A[2:0] = '001' (see Table 4). Thereafter, a

line causes the data bus to provide the 10-bit DAC

second WR pulse must be generated with the data

value on DB[9:0].

bus bits DB[11:10] = '00' and DB[9:0] containing the

actual 10-bit DAC value, with DB9 being the MSB

Table 14 shows the content of this register; the

(see Figure 35).

default value after power-up is 0x3FF (see also

Table 3).

Table 14. DAC Register Contents

DAC REGISTER CONTENT

11 10 9 8 7 6 5 4 3 2 1 0

0 0 MSB Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Figure 35. DAC Write and Read Access Timing Diagram

1 2 ... 16 17 18 19 20 21 22 23 24 25 26 ... 32 33

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ADC 2 Spezifikationen Seite 21