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Input

MUX

ADC+

ADC-

CHx1+

CHx1-

CHx0+

CHx0-

ADS7865

SBAS441C –OCTOBER 2008–REVISED APRIL 2012

www.ti.com

APPLICATION INFORMATION

GENERAL DESCRIPTION

The ADS7865 includes two 12-bit analog-to-digital

converters (ADCs) that operate based on the

successive-approximation register (SAR) principle.

The ADCs sample and convert simultaneously.

Conversion time can be as low as 406.25ns. Adding

the acquisition time of 62.5ns and an additional clock

cycle for setup/hold time requirements and skew

Figure 31. Input Multiplexer Configuration

results in a maximum conversion rate of 2MSPS.

Each ADC has a fully differential 2:1 multiplexer front-

Table 1. Fully Differential 2:1 Multiplexer

end. In many common applications, all negative input

Configuration

signals remain at the same constant voltage (for

C1 C0 ADC+ ADC–

example, 2.5V). In this type of application, the

0 0 CHx0+ CHx0–

multiplexer can be used in a pseudo-differential 3:1

mode, where CHx0– functions as a common-mode

1 1 CHx1+ CHx1–

input and the remaining three inputs (CHx0+, CHx1–,

and CHx1+) operate as separate inputs referred to

Table 2. Pseudo-Differential 3:1 Multiplexer

the common-mode input.

Configuration

The ADS7865 also includes a 2.5V internal reference.

C1 C0 ADC+ ADC–

The reference drives a 10-bit digital-to-analog

0 0 CHx0+ CHx0–

converter (DAC), allowing the voltage at the REF

OUT

0 1 CHx1– CHx0–

pin to be adjusted via the internal DAC register in

1 0 CHx1+ CHx0–

2.44mV steps. A low-noise operational amplifier with

unity-gain buffers the DAC output voltage and drives

The input path for the converter is fully differential

the REF

OUT

pin.

and provides a common-mode rejection of 72dB at

The ADS7865 offers a parallel interface that is pin-

100kHz. The high CMRR also helps suppress noise

compatible with the ADS7862. However, instead of

in harsh industrial environments.

the A0 pin of the ADS7862 that controls channel

Each of the 2pF sample-and-hold capacitors (shown

selection, the ADS7865 offers a write data input (WR)

as C

in the Equivalent Input Circuit ) is connected

pin that supports additional functions described in the

via switches to the multiplexer output. Opening the

Digital section of this data sheet (see also the

switches holds the sampled data during the

ADS7862 Compatibility section).

conversion process. After finishing the conversion,

both capacitors are pre-charged for the duration of

ANALOG

one clock cycle to the voltage present at the REF

This section discusses the analog input circuit, the

pin. After the pre-charging, the multiplexer outputs

ADCs, and the reference design of the device.

are connected to the sampling capacitors again. The

voltage at the analog input pin is usually different

Analog Inputs

from the reference voltage; therefore, the sample

capacitors must be charged to within one-half LSB for

Each ADC is fed by an input multiplexer, as shown in

12-bit accuracy during the acquisition time t

ACQ

(see

Figure 31. Each multiplexer is either used in a fully-

the Timing Characteristics).

differential 2:1 configuration (as described in Table 1)

or a pseudo-differential 3:1 configuration (as shown in

Acquisition time is indicated with the BUSY signal

Table 2). The channel selection is performed using

being held low. It starts by closing the input switches

bits C1 and C0 in the configuration register (see also

(after finishing the previous conversion and pre-

the Configuration Register section).

charging) and finishes with the rising edge of the

CONVST signal. If the ADS7865 operates at full

speed, the acquisition time is typically 62.5ns.

1 2 ... 9 10 11 12 13 14 15 16 17 18 19 ... 32 33

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