
ADS7865
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SBAS441C –OCTOBER 2008–REVISED APRIL 2012
DIGITAL DP: Deep power-down enable
('1' = device in deep power-down mode)
This section reviews the timing and control of the
ADS7865 parallel interface.
N: Nap power-down enable
('1' = device in nap power-down mode)
Configuration Register
AN: AutoNap power-down enable
The configuration register can be set by issuing a
('1' = device in autonap power-down mode)
write access on the parallel interface. The data
present on DB[11:0] are latched with the rising edge
RP: Reference power-down
of WR. The data word width of the configuration
('1' = reference is turned off)
register is 12 bits; its structure is shown in Table 4.
The default value of this register after power-up is
Table 7. A2, A1, and A0: DAC, Sequencer, and
0x000.
SW-Reset Control
A2 A1 A0 FUNCTION
Table 4. Configuration Register Map
Configuration register
0 0 0
CONFIGURATION REGISTER BIT
update only
11 10 9 8 7 6 5 4 3 2 1 0
Write to reference DAC
0 0 1
register with next access
C1 C0 R1 R0 DP N AN RP X
(1)
A2 A1 A0
Configuration register
(1) X = Don't care.
0 1 0
update only
Read from reference
Table 5. C1 and C0: Channel Selection
0 1 1 DAC register with next
access
ADC A/B
Write to sequencer
C1 C0 POSITIVE INPUT NEGATIVE INPUT
1 0 0
register
0 0 CHA0+/CHB0+ CHA0–/CHB0–
1 0 1 Device SW-reset
0 1 CHA1–/CHB1– CHA0–/CHB0–
Read from sequencer
1 0 CHA1+/CHB1+ CHA0–/CHB0–
1 1 0
register
1 1 CHA1+/CHB1+ CHA1–/CHB1–
Configuration register
1 1 1
update only
Table 6. R1 and R0: Register Update Enable
All enabled power-down features are activated by the
R1 R0 FUNCTION
rising edge of the WR pulse immediately after writing
0 0 Register update disabled
to the configuration register.
0 1 Register update enabled
Because two write accesses are required to program
Reserved for factory test (don’t
the reference DAC and the sequencer registers,
1 0
use)
these settings are updated with the rising edge of WR
1 1 Register update disabled
after the second write access. For more details, see
the Sequencer Register and Programming the
Reference DAC sections.
Copyright © 2008–2012, Texas Instruments Incorporated 17
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