
LTC4261/LTC4261-2
24
42612fd
For more information www.linear.com/LTC4261
I
2
C Interface
The LTC4261/LTC4261-2 feature an I
2
C interface to pro-
vide access to the ADC data registers and four other regis-
ters for monitoring and control of the pass FET. Figure
11
shows a general data transfer format using the I
2
C. The
LTC4261/LTC4261-2 are read-write slave devices and
support SMBus bus Read Byte, Write Byte, Read Word and
Write Word commands. The second word in a Read Word
command will be identical to the first word. The second
word in a Write Word command is ignored. The data for
-
mats for these commands are shown in Figures 12 to 15.
Using Opto-Isolators with SDA
The LTC4261/LTC4261-2 split the SDA line into SDAI (in
-
put) and SDAO (output) for convenience of opto-coupling
with the host. If opto-isolators are not used then tie SDAI
and SDAO together to form a normal SDA line. When us
-
ing opto-isolators, connect the SDAI pin to the output of
the incoming opto-isolator and connect the SDAO pin to
the input of the outgoing opto-isolator (see Figure 2). If
the SDAI and SDAO on the master controller are not tied
together, the ACK bit of SDAO must be returned back to
SDAI. If the ALERT line is used as an interrupt for the
host to respond to a fault in real time, connect the ALERT
pin to an opto-isolator in a way similar to that for the
SDAO pin as shown in Figure 2.
Figure 11. Data Transfer over I
2
C or SMBus
Figure 12. LTC4261 Serial Bus SDA Write Byte Protocol
Figure 13. LTC4261 Serial Bus SDA Write Word Protocol
Figure 14. LTC4261 Serial Bus SDA Read Byte Protocol
Figure 15. LTC4261 Serial Bus SDA Read Word Protocol
APPLICATIONS INFORMATION
START
CONDITION
STOP
ADDRESS R/W ACK DATA ACK DATA ACK
1 - 7 8 9
a6 - a0 b7 - b0 b7 - b0
1 - 7 8 9 1 - 7 8 9
P
S
S ADDRESS
0 0 1 a3:a0
FROM MASTER TO SLAVE
FROM SLAVE TO MASTER
A: ACKNOWLEDGE (LOW)
A
R: READ BIT (HIGH)
W: WRITE BIT (LOW)
S: START CONDITION
P: STOP CONDITION
COMMAND DATA
X X X X b3:b00
W
0 0 0b7:b0
A A A P
S ADDRESS
0 0 1 a3:a0
COMMAND DATA DATA
X X X X b3:b00
W
0 0 0 0
X X X X X X X Xb7:b0
A
A A A P
S ADDRESS
0 0 1 a3:a0 0 0 1 a3:a0 1 0
COMMAND S ADDRESS R A
b7:b0 1
DATA
X X X X b3:b00
W
0 0
A A A P
S ADDRESS
0 0 1 a3:a0 0 0 1 a3:a0 1 0
COMMAND S ADDRESS R A
b7:b0 1
DATA
X X X X b3:b00
W
0 0
A
0
A
b7:b0
DATA
A A P
MOSFET
TO SENSE PIN
–48V INPUT PLANE
V
EE
PLANE
LTC4261 V
EE
PIN
ALL CAPACITORS
ALL RESISTIVE DIVIDERS
ALL OPTO-ISOLATORS
I
2
C COMMON
D
G
S
R
S
VIAS
42612 F10
•
•
•
•
Figure 10. Layout Example of V
EE
Plane, –48V Input Plane and
Sense Resistor Connection
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