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LTC4261/LTC4261-2

42612fd

For more information www.linear.com/LTC4261

Configuring the PGIO Pin

Table 6 describes the possible states of the PGIO pin us-

ing the CONTROL register bits D6 and D7. At power-up

the default state is for the PGIO pin to pull low when

the second power good signal is ready

. Other uses for

the PGIO pin are to go high impedence when the sec

ond power good is ready

, a general purpose output and a

general purpose input. When the PGIO pin is conﬁgured

as a general purpose output, the status of bit C6 is sent

out to the pin. When it is conﬁgured as a general pur

pose input, if the input voltage at PGIO is higher than

1.25V

, both bit A6 in the ST

ATUS register and bit B6 in

the FAULT register are set. If the input voltage at PGIO

subsequently drops below 1.25V, bit A6 is cleared. Bit

B6 can be cleared by resetting the FAULT register as de

scribed previously.

Design Example

As a design example, consider the 200W application with

= 330µF as shown in Figure 1. The operating voltage

range is from 43V to 71V with a UV turn-off threshold of

38.5V.

The design ﬂow starts with calculating the maximum in

put current:

MAX

200W

36V

= 5.6A

where 36V is the minimum input voltage.

The selection of the sense resistor, R

, is determined by

the minimum current limit threshold and maximum input

current:

SENSE(MIN)

MAX

45mV

5.6A

= 8mW

The inrush current is set to 0.66A using C

= C

•

RAMP

INRUSH

= 330µF •

20µA

0.66A

= 10nF

The value of R

and C

are chosen to 1k and 33nF as

discussed previously.

The FET is selected to handle the maximum power dissi-

pation during start-up or an input step. The latter usually

results in a larger power due to summation of the inrush

current charging C

and the load current. For a 36V input

step, the total P

t in the FET is approximated by:

t = 36V •I

MAX

( )

•

where t is the time it takes to charge up C

t =

• 36V

INRUSH

330µF • 36V

0.66A

= 18m

which gives a P

t value of 244W

Now the P

t given by the SOA (safe operating area)

curves of candidate FETs must be higher than 244W

The SOA curves of the IRF1310NS provide for 5A at 50V

(250W) for 10ms, which gives a P

t value of 625W

s and

satisﬁes the requirement.

Sizing R1, R2 and R3 for the required UV and OV thresh

old voltages:

UV(RISING)

= 43V, V

UV(FALLING)

= 38.5V, (using

UVH(TH)

= 2.56V and V

UVH(TH)

= 2.291V)

OV(RISING)

= 72.3V, V

OV(FALLING)

= 70.7V (using

OV(TH)

= 1.77V rising and 1.7325V falling)

Layout Considerations

To achieve accurate current sensing, a Kelvin connection

is recommended (Figure 10). The minimum trace width

for 1oz copper foil is 0.02" per amp to make sure the

trace stays at a reasonable temperature. Using 0.03" per

amp or wider is recommended. Note that 1oz copper ex

hibits a sheet resistance of about 530µW/square. Small

resistances add up quickly in high current applications.

The V

pin of the LTC4261 should be connected to a

separate plane that is different from the main –48V in-

put plane. To improve noise immunity, as shown in

Figure

10, the V

connections of all capacitors, resistive

dividers, opto-isolators and I

C common must be made

directly to the local V

plane, not the –48V input plane.

APPLICATIONS INFORMATION

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