ADC 10 Bedienungsanleitung

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27-1
ADC10
ADC10
The ADC10 module is a high-performance 10-bit analog-to-digital converter.
This chapter describes the operation of the ADC10 module of the 4xx family.
The ADC10 is implemented on the MSP4340F41x2 devices.
Topic Page
16.1 ADC10 Introduction 16-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.2 ADC10 Operation 16-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.3 ADC10 Registers 16-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 27
Seitenansicht 0
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Inhaltsverzeichnis

Seite 1 - Chapter 27

27-1ADC10 ADC10The ADC10 module is a high-performance 10-bit analog-to-digital converter.This chapter describes the operation of the ADC10 module of

Seite 2 - 27.1 ADC10 Introduction

ADC10 Operation27-10 ADC10Single-Channel Single-Conversion ModeA single channel selected by INCHx is sampled and converted once. The ADCresult is writ

Seite 3 - ADC10 Introduction

ADC10 Operation27-11ADC10Sequence-of-Channels ModeA sequence of channels is sampled and converted once. The sequencebegins with the channel selected b

Seite 4 - 27.2 ADC10 Operation

ADC10 Operation27-12 ADC10Repeat-Single-Channel ModeA single channel selected by INCHx is sampled and converted continuously.Each ADC result is writte

Seite 5

ADC10 Operation27-13ADC10Repeat-Sequence-of-Channels ModeA sequence of channels is sampled and converted repeatedly. The sequencebegins with the chann

Seite 6 - 27.2.4 Auto Power-Down

ADC10 Operation27-14 ADC10Using the MSC BitTo configure the converter to perform successive conversions automaticallyand as quickly as possible, a mul

Seite 7 - Sample Timing Considerations

ADC10 Operation27-15ADC1027.2.7 ADC10 Data Transfer ControllerThe ADC10 includes a data transfer controller (DTC) to automatically transferconversion

Seite 8

ADC10 Operation27-16 ADC10One-Block Transfer ModeThe one-block mode is selected if the ADC10TB is reset. The value n inADC10DTC1 defines the total num

Seite 9 - 27.2.6 Conversion Modes

ADC10 Operation27-17ADC10Figure 27−10. State Diagram for Data Transfer Control in One-Block Transfer ModeDTC idleDTC resetn=0 (ADC10DTC1)InitializeSta

Seite 10

ADC10 Operation27-18 ADC10Two-Block Transfer ModeThe two-block mode is selected if the ADC10TB bit is set. The value n inADC10DTC1 defines the number

Seite 11 - Sequence-of-Channels Mode

ADC10 Operation27-19ADC10Figure 27−12. State Diagram for Data Transfer Control in Two-Block Transfer ModeDTC idleDTC resetADC10B1 = 0ADC10TB = 1n=0 (A

Seite 12 - Repeat-Single-Channel Mode

ADC10 Introduction27-2 ADC1027.1 ADC10 IntroductionThe ADC10 module supports fast, 10-bit analog-to-digital conversions. Themodule implements a 10-bit

Seite 13

ADC10 Operation27-20 ADC10Continuous TransferA continuous transfer is selected if ADC10CT bit is set. The DTC will not stopafter block one in (one-blo

Seite 14 - Stopping Conversions

ADC10 Operation27-21ADC1027.2.8 Using the Integrated Temperature SensorTo use the on-chip temperature sensor, the user selects the analog inputchannel

Seite 15 - ADC10 Operation

DigitalPower SupplyDecoupling100nF10uFAnalogPower SupplyDecoupling(if available)100nF10uFDVCCDVSSAVCCAVSSDigitalPower SupplyDecoupling100nF10uF100nF10

Seite 16 - One-Block Transfer Mode

ADC10 Operation27-23ADC1027.2.10 ADC10 InterruptsOne interrupt and one interrupt vector are associated with the ADC10 asshown in Figure 27−16. When th

Seite 17

ADC10 Registers27-24 ADC1027.3 ADC10 RegistersThe ADC10 registers are listed in Table 27−3.Table 27−3.ADC10 RegistersRegister Short Form Register Type

Seite 18 - Two-Block Transfer Mode

ADC10 Registers27-25ADC10ADC10CTL0, ADC10 Control Register 015 14 13 12 11 10 9 8SREFx ADC10SHTx ADC10SR REFOUT REFBURSTrw−(0) rw−(0) rw−(0) rw−(0) rw

Seite 19

ADC10 Registers27-26 ADC10MSCBit 7 Multiple sample and conversion. Valid only for sequence or repeated modes.0 The sampling requires a rising edge of

Seite 20 - DTC Transfer Cycle Time

ADC10 Registers27-27ADC10ADC10CTL1, ADC10 Control Register 115 14 13 12 11 10 9 8INCHx SHSx ADC10DF ISSHrw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(

Seite 21

ADC10 Registers27-28 ADC10ADC10DIVxBits7-5ADC10 clock divider000 /1001 /2010 /3011 /4100 /5101 /6110 /7111 /8ADC10SSELxBits4-3ADC10 clock source selec

Seite 22

ADC10 Registers27-29ADC10ADC10AE0, Analog (Input) Enable Control Register 076543210ADC10AE0xrw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0)ADC

Seite 23 - 27.2.10 ADC10 Interrupts

ADC10 Introduction27-3ADC10Figure 27−1. ADC10 Block DiagramSampleandHold10−bit SAR Divider/1 .. /8AVCCACLKMCLKSMCLKADC10SCTA0_1TA1_0Data TransferContr

Seite 24 - 27.3 ADC10 Registers

ADC10 Registers27-30 ADC10ADC10MEM, Conversion-Memory Register, Binary Format15 14 13 12 11 10 9 80 0 0 0 0 0 Conversion Resultsr0 r0 r0 r0 r0 r0 r r7

Seite 25

ADC10 Registers27-31ADC10ADC10DTC0, Data Transfer Control Register 076543210Reserved ADC10TB ADC10CT ADC10B1ADC10FETCHr0 r0 r0 r0 rw−(0) rw−(0) r−(0)

Seite 26

ADC10 Registers27-32 ADC10ADC10DTC1, Data Transfer Control Register 176543210DTC Transfersrw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0) rw−(0)DTCTr

Seite 27

ADC10 Operation27-4 ADC1027.2 ADC10 OperationThe ADC10 module is configured with user software. The setup and operationof the ADC10 is discussed in th

Seite 28

ADC10 Operation27-5ADC1027.2.2 ADC10 Inputs and MultiplexerThe eight external and four internal analog signals are selected as the channelfor conversi

Seite 29 - ADC10AE1x

ADC10 Operation27-6 ADC1027.2.3 Voltage Reference GeneratorThe ADC10 module contains a built-in voltage reference with two selectablevoltage levels. S

Seite 30

ADC10 Operation27-7ADC1027.2.5 Sample and Conversion TimingAn analog-to-digital conversion is initiated with a rising edge of sample inputsignal SHI.

Seite 31 - 76543210

ADC10 Operation27-8 ADC10Figure 27−4. Analog Input Equivalent CircuitRSRIVSVCMSP430CIVIVI= Input voltage at pin AxVS= External source voltageRS= Exter

Seite 32

ADC10 Operation27-9ADC1027.2.6 Conversion ModesThe ADC10 has four operating modes selected by the CONSEQx bits asdiscussed in Table 27−1.Table 27−1.Co

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