ADC ICX-250 Handbücher

Adc ICX-250 Spezifikationen (197 Seiten)

Marke: Adc | Kategorie: Netzwerk-Switches | Größe: 2.98 MB |

Englisch

Inhaltsverzeichnis

ST72325xx

1

Table of Contents

2

1 DESCRIPTION

7

2 PIN DESCRIPTION

8

3 REGISTER & MEMORY MAP

17

4 FLASH PROGRAM MEMORY

21

5 CENTRAL PROCESSING UNIT

24

. interrupt enable

35

7 INTERRUPTS

36

8 POWER SAVING MODES

45

9 I/O PORTS

50

10 ON-CHIP PERIPHERALS

56

Returns the buffered

75

/CC[1:0])

77

Δ OCiR =

79

Δ OCiR = Δt

79

WAKE PCE PS PIE

104

CH2 CH1EOC SPEED ADON 0 CH0

132

11 INSTRUCTION SET

136

12 ELECTRICAL CHARACTERISTICS

142

13 PACKAGE CHARACTERISTICS

174

15 KNOWN LIMITATIONS

192

16 REVISION HISTORY

196

Adc ICX-250 Bedienungsanleitung (31 Seiten)

Marke: Adc | Kategorie: Netzwerk-Switches | Größe: 1.64 MB |

Deutsche

Inhaltsverzeichnis

ICx radiation

1

ICx radiation products

2

ICx radiation product focus

3

 Physik im identiFINDER

4

 http://www.orau.org

5

Anforderungen

6

Herausforderung

6

1700 1800 1900 2000

10

Time (ns)

10

March 20, 2007

11

© BP presentation name

11

Vorteile

11

GEANT-Simulation

13

Detektorstabilisierung

14

Situation

15

Gamma-Signale

17

LED-Signale

17

 LED-Signale  Rechteckform

18

 LED/Gamma-Diskriminierung

18

Signalanalyse im identiFINDER

19

Adc ICX-250 Spezifikationen (279 Seiten)

Marke: Adc | Kategorie: Netzwerk-Switches | Größe: 2.46 MB |

Englisch

Inhaltsverzeichnis

ST72361xx-Auto

1

Contents

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Doc ID 12468 Rev 3 3/279

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Contents ST72361xx-Auto

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List of tables

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List of figures

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1 Description

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Description ST72361xx-Auto

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Kbytes)

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ST72361xx-Auto Description

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2 Register and memory map

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3 Flash program memory

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3.4 ICC interface

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3.7 Related documentation

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3.8 Register description

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4 Central processing unit

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Arithmetic management bits

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Interrupt management bits

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4.3.5 Stack pointer (SP)

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5.1 Introduction

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5.2 Main features

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5.3 Phase locked loop

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5.4 Multi-oscillator (MO)

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5.5.1 Introduction

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5.5.5 Internal watchdog reset

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Monitoring the V

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main supply

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5.6.3 Low power modes

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5.6.4 Interrupts

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5.6.5 Register description

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Application notes

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6 Interrupts

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Servicing pending interrupts

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Non-maskable sources

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Maskable sources

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Interrupts ST72361xx-Auto

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ST72361xx-Auto Interrupts

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Table 16. Interrupt mapping

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6.6 External interrupts

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6.6.2 Register description

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000000TLISTLIE

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7 Power saving modes

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7.3 Wait mode

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7.4 Halt mode

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7.5 Active halt mode

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7.6.1 Register description

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] Dividing factor

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8 I/O ports

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8.2.2 Output modes

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8.2.3 Alternate functions

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DATA BUS

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Analog alternate function

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8.3 I/O port implementation

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8.4.2 Interrupt ports

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8.4.3 Pull-up input port

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8.5 Low power modes

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8.6 Interrupts

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ST72361xx-Auto I/O ports

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9 Window watchdog (WWDG)

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9.9 Interrupts

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9.10 Register description

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Caution:

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11.1 Introduction

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11.2 Functional description

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11.2.8 Input capture function

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11.3 Register description

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Auto-Reload Register (ARTARR)

98

PWM control register (PWMCR)

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0 0 CS2 CS1 CIE2 CIE1 CF2 CF1

100

12 16-bit timer

102

12.3 Functional description

103

Returns the buffered

104

12.3.2 External clock

105

12.3.3 Input capture

106

12.3.4 Procedure

107

12.3.5 Output compare

108

12.3.6 Procedure

109

 OCiR =

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 OCiR = t

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12.3.8 One pulse mode

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112

Procedure

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12.4 Low power modes

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12.5 Interrupts

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12.6 Summary of timer modes

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12.7 Register description

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13 8-bit timer (TIM8)

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13.3.2 Input capture

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13.3.3 Output compare

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13.3.5 One pulse mode

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13.4 Low power modes

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13.5 Interrupts

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13.6 Summary of timer modes

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13.7 Register description

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13.7.7 Counter register (CTR)

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14.3.1 Functional description

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14.3.3 Master mode operation

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14.3.5 Slave mode operation

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14.5 Error flags

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14.6 Low power modes

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14.8 Register description

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14.7 Interrupts

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D7 D6 D5 D4 D3 D2 D1 D0

155

15.1 Introduction

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15.2 SCI features

156

15.3 LIN features

157

15.4 General description

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15.5.3 Serial data format

159

15.5.4 Transmitter

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Character transmission

160

Break characters

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15.5.5 Receiver

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Noise error

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Framing error

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Break character

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15.5.8 Parity control

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15.6 Low power modes

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15.7 Interrupts

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15.8.4 Data register (SCIDR)

170

15.9.1 Entering LIN mode

173

15.9.2 LIN transmission

174

15.9.3 LIN reception

175

LIN slave parity

176

15.9.4 LIN error detection

177

LIN header time-out error

178

LIN header length

179

Mute mode and errors

179

15.9.5 LIN baud rate

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Example:

183

LIN slave systems

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0000LPFR3LPFR2LPFR1LPFR0

188

Examples of LDIV coding:

189

190

16.1 Introduction

193

16.2 Main features

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16.3 General description

194

16.4 Functional description

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Data Frame

196

Next Data Frame

196

16.4.3 Receiver

198

Idle character

199

Overrun error

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16.4.7 Parity control

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16.5 Low power modes

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16.6 Interrupts

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16.8 Register description

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16.8.5 Data register (SCIDR)

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Table 80. Baud rate selection

213

17.1 Introduction

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17.2 Main features

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17.3 Functional description

214

17.3.2 A/D conversion

215

17.4 Low power modes

216

17.5 Interrupts

216

17.6 Register description

216

18 Instruction set

219

18.1.1 Inherent

220

18.1.2 Immediate

221

18.1.3 Direct

221

18.1.5 Indirect (short, long)

221

Indirect (short)

222

Indirect (long)

222

Indirect indexed (short)

222

Indirect indexed (long)

222

18.2 Instruction groups

223

18.2.1 Using a prebyte

224

19 Electrical characteristics

227

19.3 Operating conditions

230

19.4.2 On-chip peripherals

233

19.5.2 PLL characteristics

236

19.7 Memory characteristics

237

19.8 EMC characteristics

238

Electrostatic discharge (ESD)

239

19.10.2 ICCSEL/ V

247

General PCB design guidelines

254

ADC accuracy

255

Figure 123. ADC accuracy

256

20 Package characteristics

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258/279 Doc ID 12468 Rev 3

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20.3 Thermal characteristics

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21.1 Introduction

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21.2 Flash devices

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Option byte 1

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22 Development tools

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23 Important notes

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Workaround

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Doc ID 12468 Rev 3 271/279

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23.1.4 Unexpected reset fetch

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SCI mode

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Occurrence

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LIN mode

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Analysis

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23.3 ROM devices only

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24 Revision history

276

Adc ICX-250 Bedienungsanleitung (8 Seiten)

Marke: Adc | Kategorie: Netzwerk-Switches | Größe: 0.82 MB |

Englisch

Inhaltsverzeichnis

BROCADE

1

ICX 6610

1

Large Campus

4

Small/Medium-size

4

Campus

4

CLOUD-OPTIMIZED NETWORK

5

ACQUISITION

5

MAXIMIZING INVESTMENTS

5

System Architecture

6

Management

7

DATA SHEET

8

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